Integrator is the smart test station control solution that
offers superior real-time, die-by-die control and monitoring
of the test process. Regardless of the tester and prober model, Integrator can give you the advanced features
and data integrity you need to support your special test
methodologies.
Real-time control
Control the prober and tester on a die-by-die basis,
allowing ultimate flexibility and providing immediate
notification of any testing problems.
Limit total touchdowns
per die to control pad damage.
Avoid die found to be defective
during upstream inspections.
Resume testing after interruptions
where you left off, no wasted retest..
Custom applications can be driven by
die-level, wafer-level, or lot-level events.
Updates the current status of all systems
to the central floor manager / viewer.
Manual stepping and testing control
right from the Integrator screen
Yield Monitoring
Consecutive Fail and Bin monitors report test problems
early, reducing rework and yield loss.
Overall yield monitor with control
chart clearly identifies low-yielding wafers
Yield monitors can trigger stop/alarm
or automatic probe clean and retest.
Setup management
Automatically downloads setup parameters to the prober
and can even load the test program, reducing operator
error and improving process consistency.
Retrieves setup data from a central repository of setup
files.
Allows the user to choose a subset of wafers from a lot for testing
Lot setup screen can be modified to add custom data entry fields - custom data is saved with results
Can automatically set Z-height, dramatically
reducing operator-induced probe card crashes.
Monitors probe card planarity and rejects
out-of-spec cards.
Superior retest
options
Multiple Test passes - ideal
for offline inking, and retesting of specific bins.
Passes can also be used to collect results from off-line
inspection tools
Sub-pass retest - Besides using a subsequent
test pass, Integrator can retest specific bins after the
wafer completes, before unloading the wafer, as part of
a single pass
Inline retest - Specific bins are immediately
retested before the stage indexes to the next die, reducing
stepping time and giving instant recovery information
Multi-die features
Intelligent tiling algorithm calculates the minimum
number of touchdowns for any probecard layout
Each DUT site is monitored separately
for yield during multi-die probing. Yield deltas between
sites can be monitored.
Probecard layout can be
user-defined for maximum flexibility
Sample probing
Sample probe can test a sample die pattern instead
of all testable die, saving test time on high-yielding
devices. The pattern is easily configured in the control
map editor
Forced Test of edge die is also optional,
forcing selected edge die to be tested even when the sample
yield exceeds the minimum.
Sample test
by wafer - used when you want to 100% test specific wafers
in a lot while sampling the rest.
Data Management
Keeps complete wafer test history in a single file for each wafer - no lost data
Stores retest data in separate section - all test results are available, never overwritten
Export maps to SEMI G81/G85 XML format, other custom formats available
Comprehensive solution
Designed to control most of today's testers and probers.
Common data file formats for all test cells, regardless of prober and tester models.
Common simple graphical user interface for all test cells, regardless of prober and tester models.
